The placement of cells in an IC chip design during development can be summarized as encompassing four stages: During a first stage, the size of the chip is selected, and during a second stage the I/O (input/output) cells are placed. The I/O cells are the cells having pins that connect the chip to the outside world. During a third stage, placement of megacells (such as memories, large blocks of cells, etc.) is accomplished. The fourth stage comprises the placement of standard cells, such as logic cells, flip-flops, latches, etc.
Integrated circuits are used in a wide range electronic devices produced by a large number of device manufacturers. In practice, ICs are seldom manufactured (fabricated) by the electronic device manufacturer. Instead ICs are manufactured by an IC foundry to the specifications of the electronic device manufacturer. The design of the IC is usually the result of corroboration between the device manufacturer and the IC foundry. The first stage of choosing the size of the chip is usually performed by the device manufacturer so that the chip fits within the electronic device. The second stage of placement of I/O cells is also often performed by the device manufacturer, usually in close corroboration with the foundry, to meet the requirements of device form, fit and function. The third and fourth stages are performed by an IC developer, usually to meet the foundry's processes. In most cases the developer first places the megacells and then finishes the process of chip design by placing other cells using computer tools, usually supplied by the foundry.
The third stage, namely megacell placement, is the subject of the above-identified Andreev et al. application. The fourth stage, the placement of standard cells, is the subject of the present invention.
Consider a chip with a given outline and which contains only I/O cells, megacells (such as memories, large blocks of cells, etc.), and standard cells (namely logic cells and flip-flops). Assume further that the I/O cells and megacells have already been placed, such that their coordinates are fixed. Thus, the first three stages of the floorplan have been completed. As shown in FIG. 1, the layout of such a partially completed chip floorplan 10 includes I/O cells 12 and megacells 14, defining regions 16 where standard cells may be placed. Regions 16 can be characterized as composed of rectangular regions REG1, REG2, . . . , REGM, where M≧1).
Consider that N standard cell modules are to be placed into regions REG1, REG2, . . . , REGM, where N≧1, and that some standard cells belong to one of the standard cell modules MOD1, MOD2, . . . , MODN, whereas other standard cells do not belong to any standard cell module. The problem addressed by the present invention is the placement of each standard cell module MODi (1≦i≦N) into some region REGPLACE(i) where 1≦place(i)≦M, such that a) the total area of the standard cell modules placed in any region is not more than the area of the region, and b) timing restrictions are accounted for.
The present invention is particularly useful for floorplan development of chips using technology that segments total chip area into regions of various types, such as regions for placement of megacells and I/O cells and regions for placement of standard cells. Examples of such technology include RapidChip® technology available from LSI Logic Corporation or/and FPGA.